1. Field of the Invention
The present invention relates to a semiconductor memory device including a status register for storing various operation states of a memory array capable of data write or erase, and an information device using the same, for example, a computer or an information mobile device.
2. Description of the Related Art
One of semiconductor memory devices capable of storing information even after supply of power is stopped is a flash memory (or a flash EEPROM (Electrically Erasable and Programmable ROM)). The flash memory has a function of electrically erasing data in memory cells in the entire chip or a certain area in the chip (sector or block) in globally. Thus, the flash memory allows the area of a memory cell to be as small as that of an EPROM (Erasable and Programmable ROM).
In such a flash memory (nonvolatile semiconductor memory device), the memory arrays are in a greater number of operation states (for example, write, block erase, global erase of the entire chip, and read of the status register) than in a RAM (Random Access Memory) capable of performing information read and write within a short time period. In conventional EPROM or EEPROM, such a great number of operation states cannot correspond, one to one, to combinations of external control signals (for example, a chip enable signal (/CE), a write enable signal (/WE) and an output enabler signal (/OE)). The reason is that the number of control signals are not sufficient for all the operation states of the memory arrays. Therefore, it is necessary to add new control signals.
However, addition of the new control signal lines results in less ease in use. Therefore, a system of performing controls by commands is mainly used today.
FIG. 9 is a block diagram showing a partial structure of a conventional nonvolatile semiconductor memory device 100. As shown in FIG. 9, the nonvolatile semiconductor memory device 100 includes a memory array 120, a command state machine (CSM) 102, a write state machine (WSM) 103, a row decoder 104, a column decoder 105, a block selection circuit 106, a status register (SR) 107, block protect setting sections (BPs) 108, a data switching circuit 109, a block status register (BSR) 110, a data bus 112, an address bus 113, a reset signal input line 114, an erase/write voltage generation circuit 115, and a sense amplifier 116.
The memory array 120 includes a plurality of erase blocks 101 (erase blocks 1 through n) each including a plurality of memory cells.
The command state machine 102 (hereinafter, referred to as the xe2x80x9cCSM 102xe2x80x9d) decodes an input command 111 and transfers the decoding result (for example, block erase or write) to the write state machine 103. The CSM 102 is connected to, for example, a command input line and a reset signal input line 114. In synchronization with the command 111 or a reset signal R externally input to the CSM 102, the input levels of a chip enable signal /CE, a write enable signal/WE, an output enable signal /OE and the like change.
The write state machine 103 (hereinafter, referred to as the WSM 103) executes various operations (for example, block erase/write) in accordance with the decoding result of the input command 111. More specifically, when a block which is selected by the block selection circuit 106 (described below) is not in, for example, an erase prohibition state (a block lock state), the WSM 103 can globally erase the data in the block. When the block is in the block lock state, the WSM 103 does not rewrite the data stored in the block.
The row decoder 104 sequentially selects word lines (not shown) in the memory array 120 so as to electrically connect each of the memory cells in each row connected to the selected word line to a corresponding bit line.
The column decoder 105 selects one of a plurality of bit lines (not shown) in the memory array 120 so as to connect the selected bit line to the sense amplifier 116 (described below).
The block selection circuit 106 selects one of the n number of erase blocks 101.
The status register 107 (hereinafter, referred to as the xe2x80x9cSR 107xe2x80x9d) stores the data representing an operation state of the memory array 120 (for example, block erase/write).
The block protect setting sections 108 (hereinafter, referred to as the xe2x80x9cBPs 108xe2x80x9d) are each a control bit for locking or unlocking an erase block 101 corresponding thereto. Data indicating whether each erase block 101 is locked or unlocked is stored in the block status register 110 (hereinafter, referred to as the xe2x80x9cBSR 110xe2x80x9d) of each erase block 101 as described below.
The data switching circuit 109 selects one of data stored in the memory array 120, data stored in the SR 107 or data stored in the BSR 110 to be read.
The BSR 110 corresponding to each erase block 101 stores data indicating whether the corresponding erase block 101 is in a locked state or an unlocked state. The BSR 110 also stores data indicating which erase block 101 is selected by an address externally designated.
The command 111 is a command signal as a control instruction which is input by the user. The command 111 instructs execution of various operations (for example, block erase/write).
The data bus 112 has a 16-bit width in order to allow data D to be transferred between the CSM 102 or the data switching circuit 109 and external devices. The data bus 112 is not limited to having a 16-bit width, and may have, for example, a 24-bit or 32-bit width.
The address bus 113 receives an address signal A, and the reset signal line 114 receives a reset signal R.
The erase/write voltage generation circuit 115 is provided for erase or write. The erase/write voltage generation circuit 115 receives a prescribed voltage from an external power supply Vcc, and when necessary, generates a high voltage of about 12 V. For executing a negative gate erase, the erase/write voltage generation circuit 115 generates a negative potential.
The sense amplifier 116 amplifies the bit line voltage selected by the column decoder 105 so as to sense information stored in the selected memory cell.
The nonvolatile semiconductor memory device having the above-described structure operates as follows.
When the user inputs the command 111, the CSM 102 decodes the command 111 and outputs the decoding result to the WSM 103. The WSM 103 executes a memory operation in accordance with the command 111 (for example, block erase/write).
For example, a block erase operation is usually performed as follows. First, one of the erase blocks 101 to be erased is selected, and data xe2x80x9c0xe2x80x9d is written in all the memory cells (not shown) in the selected erase block 101 (i.e., threshold voltage Vth in the memory cell transistor is changed to a HIGH level).
Next, when the threshold voltage Vth of all the memory cells in the selected erase block 101 becomes equal to or higher than a prescribed value, data stored in the memory cells in the erase block 101 is globally erased (i.e., the threshold voltage Vth is changed to a LOW level).
This series of operations are controlled by the WSM 103, and the result of the operations (for example, the result that the data in the erase block 101 has been erased) is stored in the SR 107 and in the corresponding BSR 110 as data which represents the operation state of the memory array 120.
In order to read the data stored in the SR 107 and the data stored in the BSR 110, the conventional flash memory needs to be operated as follows.
While the WSM 103 is executing a command, 8-bit data stored in the SR 107 can be read, not the data stored in the memory array 120, by changing the chip enable signal /CE and the output enable signal/OE to a LOW (active) level so as to perform a read operation. Even when a 16-bit data bus is used, the data stored in the SR 107 is output to the lower 8 bits and the upper 8 bits are not used, regardless of the designated address.
Data stored in the SR 107 will be described using a part of FIG. 3 (described below). As shown in FIG. 3, the SR 107 stores, for example, the following data which represents the operation states of the memory array 120: WSMS (indicating whether the WSM 103 is in a ready state or a busy state), ESS (indicating whether WSM 103 is in an erase interrupt state, or an erasing or erase completion state), ES (indicating whether WSM 103 is in a block erase error state or in a block erase success state), DWS (indicating whether WSM 103 is in a data write error state or a data write success state), VPPS (indicating whether WSM 103 is in a VPP low potential detection or operation stop state or in a VPP normal state). The above-mentioned data is stored in bits 7 through 3.
For example, in bit 7 of the SR 107, a bit representing the operation state of the WSM 103 (WSMS bit) is stored. The value xe2x80x9c1xe2x80x9d of the WSMS bit represents the ready state, and the value xe2x80x9c0xe2x80x9d of the WSMS bit represents the busy state (in execution).
In bit 6 of the SR 107, a bit representing the erase interrupt state (ESS bit) is stored. The value xe2x80x9c1xe2x80x9d of the ESS bit represents the erase interrupt state, and the value xe2x80x9c0xe2x80x9d of the ESS bit represents the erasing or erase completion state.
In bit 5 of the SR 107, a bit representing the block erase (ES bit) is stored. The value xe2x80x9c1xe2x80x9d of the ES bit represents the block erase error state, and the value xe2x80x9c0xe2x80x9d of the ES bit represents the block erase success state.
In bit 4 of the SR 107, a bit representing the data write state (DWS bit) is stored. The value xe2x80x9c1xe2x80x9d of the DWS bit represents the data write error state, and the value xe2x80x9c0xe2x80x9d of the DWS bit represents the data write success state.
In bit 3 of the SR 107, a bit representing the VPP state (VPPS bit) is stored. The value xe2x80x9c1xe2x80x9d of the VPPS bit represents the VPP low potential detection or operation stop state, and the value xe2x80x9c0xe2x80x9d of the VPPS bit represents the VPP normal state.
In the conventional flash memory, bits 2 through 0 of the SR 107 may be different from those shown in FIG. 3. In the conventional flash memory, bits 2 through 0 are reserved for future expansion functions, and therefore need to be masked when the SR 107 is polled.
When using the data stored in the SR 107, it is necessary to first check the state of external terminals RY/BY# provided for outputting the WSMS bit or information equivalent to the WSMS bit so as to confirm that the operation (for example, erase interrupt, erase, or data write) has been completed. Then, it is necessary to confirm that the corresponding status bit (the ESS bit, ES bit or DWS bit) represents success.
When the DWS bit and the ES bit are set to be xe2x80x9c1xe2x80x9d in the block erase operation, this means that a wrong command sequence has been input. In this case, it is necessary to clear the data stored in each bit and perform the operation again.
The VPPS bit represents the VPP level, but does not continuously represent the VPP level. The WSM 103 checks the VPP level only after the command sequence for data write or erase is input, and shows the result.
In the case where the BSR 110 representing the state of each erase block is built in the nonvolatile semiconductor memory device 100, a read command for the BSR 110 is issued so as to read the 8-bit data stored in the BSR 110. Even when the 16-bit bus is used, the upper 8 bits of the bus are not used and the data in the BSR 110 corresponding to the selected address bus is output to the lower 8 bits of the bus.
A flash memory having a function of two-chip memory arrays built in one package is available today. As an improvement over this type of flash memory, another flash memory has been developed in which while data is written to or erased from a one-chip memory array (e.g., a first memory array), data can be read from the memory array of the other chip (e.g., a second memory array).
The above-described conventional flash memories have the following problems.
The number of bits of one status register for representing the status of the memory chip is limited. Therefore, the number of statuses which can be represented by one status register is restricted.
For example, one chip flash memory including a plurality of status registers is operated as follows in order to identify the state of the memory chip after, for example, data is erased from or written to the memory chip. The chip enable signal CE# and the output enable signal OE# are changed to a LOW level. Then, information stored in the status register can be read. However, it cannot be determined., only based on the information thus obtained, from which status register the information has been read.
In addition, when data is transferred to the flash memory from other memory chips out side or in side the package, the status register cannot show which address is now being processed by the data transferred. Namely, while a command is being executed for a certain range of addresses, it cannot be identified which address among the certain range of addresses is now being processed.
According to one aspect of the invention, a semiconductor memory device in which an input command controls an operation includes a command state machine for decoding the input command and outputting the decoding result; a plurality of status registers for storing state information of the semiconductor memory device; a first switching circuit for receiving data from the plurality of status registers, and selectively outputting the data from at least one of the plurality of status registers to a first data bus; and a second switching circuit for receiving the data on the first data bus and data from a sense amplifier, and selectively outputting either one of data to a second data bus. At least the first switching circuit, among the first and second switching circuits, is controlled by the decoding result output by the command state machine.
In one embodiment of the invention, at least one of the plurality of status registers includes identification information for exclusively identifying the status register.
In one embodiment of the invention, at least one of the plurality of status registers includes information on an address which is currently being processed with an operation designated by the input command.
In one embodiment of the invention, at least one of the plurality of status registers includes information on an address which is currently being processed with an operation designated by the input command.
In one embodiment of the invention, the semiconductor memory device includes a control section for, after the command is input, controlling the state information, stored in the plurality of status registers, to be externally output in accordance with a read control signal which is input to an external control terminal.
In one embodiment of the invention, the first data bus has a width which is equal to or less than a width of the second data bus.
According to another aspect of the invention, a semiconductor memory device, including a plurality of memory arrays which are independently operable and having a function of transferring data between the plurality of memory arrays, includes a plurality of status registers for storing state information of the plurality of memory arrays; a first switching circuit for receiving data from the plurality of status registers, and selectively outputting the data from at least one of the plurality of status registers to a first data bus; and a second switching circuit for receiving the data on the first data bus and data from a sense amplifier, and selectively outputting either one of the data to a second data bus.
In one embodiment of the invention, an input command controls an operation, the semiconductor memory device further comprising a command state machine for decoding the input command and outputting the decoding result, wherein the first switching circuit and the second switching circuits are controlled by the decoding result output by the command state machine.
In one embodiment of the invention, the plurality of status registers include a first status register group including at least one status register for storing state information regarding an operation common to the semiconductor memory device, and a second status register group including at least one status register for storing state information regarding a data transfer operation between the plurality of memory arrays.
In one embodiment of the invention, the plurality of status registers include a first status register group including at least one status register for storing state information regarding an operation common to the semiconductor memory device, and a second status register group including at least one status register for storing state information regarding a data transfer operation between the plurality of memory arrays.
In one embodiment of the invention, the first and second status register groups each include information which identifies whether the status register belongs to the first status register group or the second status register group.
In one embodiment of the invention, the first and second status register groups each include information which exclusively identifies the respective status register.
In one embodiment of the invention, the first and second status register groups each include information which exclusively identifies the respective status register.
In one embodiment of the invention, the second status register group includes information on an address which is currently being processed with an operation designated by the command.
In one embodiment of the invention, the semiconductor memory device includes a control section for, after the command is input, controlling the state information, stored in the first and second status register groups, to be externally output in accordance with a read control signal which is input to an external control terminal.
In one embodiment of the invention, the semiconductor memory device further includes a write state machine for receiving the decoding result of the command output by the command state machine and controlling execution of an operation designated by the command based on the decoding result, wherein the second status register group includes information which indicates whether or not the write state machine is currently executing the data transfer operation between the plurality of memory arrays.
In one embodiment of the invention, at least one of the plurality of memory arrays is capable of being accessed at a higher speed than other memory arrays. The at least one memory array capable of being accessed at a higher speed is divided into a plurality of pages, which are memory areas. The second status register group includes information which represents the page which is currently being involved in the data transfer operation between the at least one of the plurality of memory arrays capable of being accessed at a higher speed and the other memory arrays.
In one embodiment of the invention, the at least one of the plurality of memory arrays capable of being accessed at a higher speed is a static random access memory, and the other memory arrays include a nonvolatile semiconductor memory device capable of electrically writing and erasing data.
In one embodiment of the invention, the second status register group includes data transfer result information which indicates whether or not the data transfer operation between the plurality of memory arrays has successfully been completed.
In one embodiment of the invention, the semiconductor memory device further includes a supply voltage detection section for detecting a supply voltage, wherein the second status register group includes information which indicates whether or not the supply voltage is abnormal while the data transfer operation between the plurality of memory arrays is being executed.
In one embodiment of the invention, the second status register group includes information which indicates whether the data transfer operation between the plurality of memory arrays is currently being executed or interrupted.
In one embodiment of the invention, the semiconductor memory device further includes an information protection section for protecting stored information against a rewrite operation to the plurality of memory arrays, wherein the second status register group includes information which represents a protection state against the rewrite operation and also indicates that the data transfer operation has been interrupted by detecting the protection state when the command instructs the data transfer operation to the memory arrays which are protected against the rewrite operation.
In one embodiment of the invention, the first data bus has a width which is equal to or greater than a bit width of the first status register group or the second status register group.
In one embodiment of the invention, the first data bus has a width which is equal to or greater than a sum of a bit width of the first status register group and a bit width of the second status register group.
In one embodiment of the invention, the first data bus has a width which is equal to or less than a width of the second data bus.
According to still another aspect of the invention, an information device for performing at least one of a data transfer operation and a memory operation using any of the above-described semiconductor memory device.
As described above, a semiconductor memory device of the present invention includes a plurality of status memory sections, so that various operation states of the semiconductor memory device can be represented. The plurality of status memory sections are selected by the decoding result of the input command, without requiring a read control instruction (command) for each status. Therefore, the conventional status reading method is usable for the semiconductor memory device of the present invention.
By outputting contents stored in the plurality of status memory sections in combination, various operation states of a grater number of memory chips (memory arrays) can be represented. In this case also, the plurality of status memory sections are selected by the decoding result of the input command, without requiring a read control instruction (command) for each status. Therefore, the conventional status reading method is usable for the semiconductor memory device of the present invention.
In addition to confirming the busy state of the write state machine by bit 7 as in the conventional status memory section, the semiconductor memory device according to the present invention can identify the address which is currently being processed with the memory operation by a plurality of bits, for example, bit 2 and bit 1. The address(es) from which data can be read is identified before all the addresses are processed with the operation based on the command. Such an address can be identified only by reading the data in the status register as in the conventional device, with no special command or input/output bus being required. Therefore, the conventional status reading method is usable for the semiconductor memory device in the third example.
When one of the plurality of statuses is read without using any special command for reading data stored in the status memory section, the status data which is currently being read is identified by the bits of the status memory section. Therefore, the conventional status reading method is usable for the semiconductor memory device of the present invention.
Since there are two status memory sections for a command status and a transfer status, a greater number of operation states can be represented. Either the command status mode or the transfer status mode is selected in accordance with the command. Which mode is being used can be identified by the bits in the status memory section. Since each status memory section is selected by the command, any special command for reading the status register is not necessary. Therefore, the conventional status reading method is usable for the semiconductor memory device of the present invention. In the transfer status register mode, the address which is currently being involved in the data transfer can be identified. Therefore, even before data transfer from/to all the addresses is completed, data can be transferred to the address, from which data has been transferred.
Thus, the invention described herein makes possible the advantages of providing a semiconductor memory device for representing a larger number of operation states of a memory array with status registers, and an information device using such a semiconductor memory device.
These and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures.